A K-Band adaptive-bias power amplifier with enhanced linearizer using 0.18-µm CMOS process

A new topology of power amplifier (PA) is developed in 0.18-μm CMOS. The topology adopts the adaptive bias and pre-distortion linearizer simultaneously. The design of this PA takes back-off efficiency, linear output power, and quiescent power consumption into consideration. After linearization, the proposed PA achieves 6.8% PAE at 6-dB backoff from P_1dB, 14.1% PAE at OP_1dB, and high linear output power 9.2 dBm with third-order intermodulation distortion (IMD3) of -40 dBc. This circuit shows good performance compared with the published PAs in 0.18-μm CMOS and suitable for high data rate transmission applications.