A Power-Aware Algorithm for the Design of Reconfigurable Hardware during High Level Placement

The popularity of reconfigurable logic devices and portable hardware demands ever increasingly power saving schemes for low power designs. This paper looks at the CAD design process of reconfigurable devices and presents a novel method to gain power savings during the placement stage of the CAD flow. The proposed system modeled the number of switches used in the circuit and employed simulated annealing algorithm to reduce the overall routing power. The system was tested against 8 large benchmark circuits. It was able to achieve a routing power saving of up to 18% compared with cases without modeling the switches.