• DocumentCode
    3285752
  • Title

    A Novel Hardware Architecture for Self-adaptive Systems

  • Author

    Casas, José Antonio ; Moreno, Juan Manuel ; Madrenas, Jordi ; Cabestany, Joan

  • Author_Institution
    Tech. Univ. of Catalunya (UPC), Catalunya
  • fYear
    2007
  • fDate
    5-8 Aug. 2007
  • Firstpage
    592
  • Lastpage
    599
  • Abstract
    This article focuses at studying the implementation of the self-configuration concept on a novel unconventional hardware architecture. This proposed programmable architecture implements self-placement and self-routing which, due to its intrinsic design, enable the development of systems with self-configuration, self-repair and/or fault tolerance capabilities [1],[2]. For scalability issues, the architecture has been defined as a regular array of homogeneous elements. It is able to analyze and modify its own circuits. This means that the functionality can be modified and improved over time, leading to more versatile designs. The system can check for faulty cells or regions and simply work around them. Those cells can be marked as bad regions so the system can keep working. This permits to deal with imperfectly-manufactured cell arrays, which is a key issue in the extremely complex systems envisioned for the future micro and nano technologies.
  • Keywords
    field programmable gate arrays; performance evaluation; fault tolerance; hardware architecture; programmable architecture; self-adaptive systems; Assembly; Circuit faults; Constraint optimization; Distributed control; Fault tolerant systems; Field programmable gate arrays; Hardware; Integrated circuit interconnections; Logic gates; Scalability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Adaptive Hardware and Systems, 2007. AHS 2007. Second NASA/ESA Conference on
  • Conference_Location
    Edinburgh
  • Print_ISBN
    978-0-7695-2866-3
  • Type

    conf

  • DOI
    10.1109/AHS.2007.11
  • Filename
    4291972