A LVS verification flow for hybrid digital-analog integrated circuits

In the design of hybrid digital-analog integrated circuits, with the circuit design becoming increasingly large scale, hierarchical design techniques have become more acceptable for most designers. However, the occurrence of layout LVS (Layout versus Schematic) error could be sharply increased. Debugging these errors one by one will take designer a large amount of time and energy, which is intolerable. In order to overcome this problem, in this paper, a process of LVS based on hierarchical design techniques is introduced. With Calibre verification tool, it´s successfully used in the layout verification of Pipeline ADC, which greatly reduces the verification time, improving the layout of the verification process.