Novel simple decision stage of Pan & Tompkins QRS detector and its FPGA-Based implementation

The QRS detection is the entry point for almost all the ECG applications. This paper presents a new simple and efficient FPGA-Based implementation of the well-known Pan and Tompkins QRS detection algorithm. The design is implemented using Xilinx design tool, System Generator for DSP. In the authors´ view, the specific features, that is simplicity, efficiency and authenticity, of the proposed model lies in the fact that the threshold value is updated for the next peak detection, from the previous smallest peak; in addition, the model is entirely designed simply with MCode blocks. The hardware design is tested with five 30 minutes data records obtained from the MIT-BIH Arrhythmia database. Its accuracy exceeds 96%, knowing that four records among the five represent the worst cases in the database.