Novel Palmo analogue signal processing IC design techniques

Introduces and analyses a novel technique for implementing programmable analogue hardware. Novel programmable Palmo circuits have been introduced which have low switching noise, low THD, and may be configured to perform many signal processing functions. An initial test chip has demonstrated the viability of the approach and aided in understanding the practical application of the technique. This has led to new ideas for the implementation of the Palmo building blocks to reduce THD and improve overall programmability and performance. Such circuits are ideal for field programmable analogue array (FPAA) cells. The new Palmo circuit blocks have a dedicated 6-bit current DAC and 3-bit programmable capacitor array giving 9 bits of programmability per cell. Cell interconnect to local neighbours or to pads further enhances programmability and high frequency performance. Dedicated static RAM is used to store the cell parameters and interconnect-which may also be dynamically reconfigured. A new improved comparator is under development to reduce harmonic distortion at high frequencies. These circuits are currently being designed and a new chip is to be fabricated in the near future