High performance binarizer for H.264/AVC CABAC

The CABAC (Context Adaptive Binary Arithmetic Coding) in the H.264/AVC standard, consists of binarizer, arithmetic encoder, and bit generator. In this paper, we propose a high performance binarizer and focus on accelerating the binarization and context index generation processes. Because most SEs (Syntax Elements) generate less than 4 bins for each, the throughput of the one-by-one binarization for SEs can not support the subsequent arithmetic encoder reported with the encoding ability of multiple bins/clock cycle. The majority of the resulting bins are produced by the SEs of motion vector difference, intra prediction modes, and coefficients, therefore, accelerating the binarization for these SEs is efficient to improve the binarization throughput. After analyzing the SEs in the bit stream, we found that these SEs are next to each other in advent order and some of them can be paired and processed in parallel. In this paper, a SEs-pairing scheme is proposed and the binarization throughput of 4.11 bins/clock cycle is achieved. The corresponding implementation architecture is also proposed. After implemented in Verilog-HDL and synthesized with Synopsys Design Compiler using 90 nm libraries, the proposal consumes about 19.3 K gates and 22.8 Kbits RAM working at the frequency of 250 MHz.