A LDO regulator with slew-rate enhancement circuit for low-power SoC

Author

Qianneng, Zhou ; Hongjuan, Li ; Tan, Min

Author_Institution

Chongqing Univ. of Posts & Telecommun., Chongqing, China

fYear

2011

fDate

15-17 April 2011

Firstpage

32

Lastpage

35

Abstract

A low dropout (LDO) regulator is designed in this paper. By adopting a slew rate enhancement circuit, the slew rate of the LDO output is obviously improved when the load current is suddenly switched from low to high. Moreover, employing a simple bias circuit, the architecture of the LDO regulator is simple, and can be fabricated by conventional CMOS technology. The LDO regulator is designed and simulated in CSMC 0.5μm CMOS process. Simulation results show that the PSRR of the LDO regulator at 100Hz, 1kHz and 10kHz achieves, respectively, -76dB, -70dB and -52dB at room temperature and V_dd=2V. The circuit can provide an output voltage of 1.2V with a variation of 8mV in a load current range from 0 to 50mA. The deviation of the output voltage is within 11mV when power supply voltage V_dd changes from 1.4V to 6V.

Keywords

CMOS integrated circuits; low-power electronics; system-on-chip; CMOS technology; LDO regulator; current 0 mA to 50 mA; frequency 1 kHz; frequency 10 kHz; frequency 100 Hz; low dropout regulator; low-power SoC; size 0.5 mum; slew-rate enhancement circuit; voltage 1.2 V; voltage 1.4 V to 6 V; voltage 11 mV; voltage 2 V; CMOS integrated circuits; Generators; Logic gates; Regulators; Simulation; System-on-a-chip; Voltage control; Control Voltage generator; Low dropout regulator; Power Supply Rejection; Slew Rate Enhancement Circuit;

fLanguage

English

Publisher

ieee

Conference_Titel

Electric Information and Control Engineering (ICEICE), 2011 International Conference on

Conference_Location

Wuhan

Print_ISBN

978-1-4244-8036-4

Type

conf

DOI

10.1109/ICEICE.2011.5777973

Filename

5777973