Title :
System-level performance optimization and benchmarking for on-chip graphene interconnects
Author :
Chenyun Pan ; Naeemi, Azad
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
In this paper, graphene interconnects are analyzed and benchmarked against conventional copper wires, indicating the advantage of using graphene at a short wire length or being driven by a device with a large output resistance. For the first time, a system-level optimization of graphene interconnects is performed for both single- and multi-core chips. It is found that under the same power density and die size area, an optimized multi-core processor using graphene as short interconnects can provide up to 25% and 55% improvements in throughput and energy × execution time per instruction, respectively.
Keywords :
circuit optimisation; copper; graphene; integrated circuit interconnections; C; copper wire; die size area; multicore chip; on-chip graphene interconnect; output resistance; power density; single-core chip; system-level optimization; system-level performance optimization; Capacitance; Copper; Graphene; Integrated circuit interconnections; Parallel processing; Throughput; Wires; Graphene; interconnect; system-level optimization;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2012 IEEE 21st Conference on
Conference_Location :
Tempe, AZ
Print_ISBN :
978-1-4673-2539-4
Electronic_ISBN :
978-1-4673-2537-0
DOI :
10.1109/EPEPS.2012.6457837
