Title :
Comparison of TSV-based PDN-design effects using various stacking topology methods
Author :
Charles, Guy ; Franzon, Paul D.
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Abstract :
In this study, we estimate, compare and analyze the PDN effects of four chip-stacking topologies. The chip-stacking topologies are: (1) F2B; (2) F2F; (3) B2F; and (4) B2B. The arrangement of various on-chip interconnect elements based on the chip-stacking topologies specific to the design of 3D IC-PDN, varies in impedance properties. To reduce the impedance effects NMOS decap unit cells are integrated into PDN system to suppress 3D-SSN. Conclusively, the results of the case study indicate B2F and F2B die stacking topologies results in lower impedance effects relative to F2F topology.
Keywords :
integrated circuit interconnections; network topology; three-dimensional integrated circuits; 3D IC-PDN; 3D-SSN; B2B; B2F; F2B; F2F; NMOS decap unit cells; TSV-based PDN-design effects; chip-stacking topologies; on-chip interconnect elements; power delivery network; Impedance; Metals; Silicon; Stacking; System-on-a-chip; Through-silicon vias; Topology; 3D IC; B2F and B2B; F2B; F2F; Power delivery network (PDN); Redistribution layer (RDL); SSN; Through silicon via (TSV); target impedance;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2012 IEEE 21st Conference on
Conference_Location :
Tempe, AZ
Print_ISBN :
978-1-4673-2539-4
Electronic_ISBN :
978-1-4673-2537-0
DOI :
10.1109/EPEPS.2012.6457848
