High-performance hardware for function generation

High speed elementary function generation is crucial to the performance of many DSP applications. The paper presents an interpolator architecture for generating elementary functions based on an optimal trade off between the use of memory modules and computational circuits. The architecture uses one third less memory than alternative schemes while incurring no time penalty and minimal additional circuit. The pipelined design has a throughput of generating one functional value per clock cycle, and a latency of two clock cycles