FPGA implementation of the FDTD data flow machine

Author

Matsuoka, S. ; Kawaguchi, H.

Author_Institution

Dept. of Electr. & Electron. Eng., Muroran Inst. of Technol., Japan

fYear

2003

fDate

15-17 Oct. 2003

Firstpage

418

Lastpage

419

Abstract

Aiming at ultra high performance computing in electromagnetic field simulation, the authors have been working on the development of an FDTD dedicated computer (Kawaguchi, H. et al., IEEE Trans. Magn., vol.38, no.2, p.689-62, 2002). The FDTD method is a very simple algorithm, which can be utilized by a relatively small digital circuit. The authors have already presented a basic design and logic simulation of. the dedicated computer architecture. This paper presents an implementation of the FDTD dedicated computer by means of the FPGA whose design and logic simulation have already been done using VHDL design software.

Keywords

computational electromagnetics; computer architecture; field programmable gate arrays; finite difference time-domain analysis; logic CAD; FDTD data flow machine; FPGA implementation; VHDL; computer architecture; digital circuit; electromagnetic field simulation; Circuit simulation; Computational modeling; Computer simulation; Digital circuits; Electromagnetic fields; Field programmable gate arrays; Finite difference methods; High performance computing; Logic design; Time domain analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Communication Technology, 2003. IEEE Topical Conference on

Print_ISBN

0-7803-8196-3

Type

conf

DOI

10.1109/WCT.2003.1321585

Filename

1321585