Title :
Scan testing of latch arrays
Author :
Hui, Michael M Y ; Nadeau-Dostie, Benoit
Abstract :
A novel scan-based test method that allows latch-based arrays to be fully tested using conventional scan software tools is described. Very little support circuitry and simple modeling are required. Several useful applications of the method are described. The method was used on several production chips.<>
Keywords :
boundary scan testing; logic arrays; logic testing; production testing; latch arrays; production chips; scan-based test method; software tools; Application software; Circuit testing; Combinational circuits; Flip-flops; Intelligent networks; Latches; Sequential analysis; Shift registers; Software testing; Software tools;
Conference_Titel :
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-7803-0623-6
DOI :
10.1109/VTEST.1992.232720
