A methodology for the insertion of a hierarchical and boundary-scan compatible self test

Author

Haberl, Oliver F. ; Kropf, Thomas

Author_Institution

Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany

fYear

1992

fDate

7-9 April 1992

Firstpage

37

Lastpage

42

Abstract

A methodology is presented, which automatically embeds a self test architecture into hierarchically designed circuits. For each module of the design hierarchy the automatic method for the insertion of self test registers as well as the synthesis of a test control unit is presented. These self testable modules are then combined for arbitrary hierarchy levels using test management units. The concept is embedded within the boundary-scan architecture and the implementation has been integrated into a commercial design framework.<>

Keywords

boundary scan testing; built-in self test; integrated logic circuits; logic testing; arbitrary hierarchy levels; boundary-scan compatible self test; design framework; hierarchically designed circuits; self test architecture; self test registers; self testable modules; test control unit; test management units; Automatic testing; Built-in self-test; Circuit testing; Fault tolerance; Hardware; Integrated circuit synthesis; Logic testing; Performance evaluation; Registers; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE

Conference_Location

Atlantic City, NJ, USA

Print_ISBN

0-7803-0623-6

Type

conf

DOI

10.1109/VTEST.1992.232721

Filename

232721