The split boundary scan register technique for testing board interconnects

Presents a new approach to testing board interconnects, on a board containing three-state nets and with chips equipped with the boundary scan architecture. The proposed technique reduces the test time, test vector size, and requires an order independent test set at the expense of minimal hardware overhead to the ANSI/IEEE Std1149.1-1990 standard. Although most of the algorithms developed so far can be used to test boards under this scheme, the authors have concentrated on the walking 1´s and 0´s for the purpose of presenting this technique. This test can be applied with a reduced time complexity for test generation and application. Furthermore, with local response compaction this scheme can easily be used for BIST implementation, resulting in the application of walking 1/0 in linear time.<>