A design for testability scheme to reduce test application time in full scan

Author

Pradhan, Dhiraj K. ; Saxena, Jayashree

Author_Institution

Massachusetts Univ., Amherst, MA, USA

fYear

1992

fDate

7-9 April 1992

Firstpage

55

Lastpage

60

Abstract

Full scan is a widely accepted design for testability technique for sequential circuits. However, the test application time required by full scan could be high because of the necessity to scan in and scan out test vectors. In this paper, a hybrid scheme is presented that aims to reduce test application time in circuits with full scan. The proposed scheme exploits the inherent sequential nature of the circuit in conjunction with the additional controllability and observability available through full scan. Also, it is shown that the hybrid scheme has an additional advantage of being suited for testing transition faults.<>

Keywords

boundary scan testing; design for testability; logic testing; sequential circuits; controllability; design for testability; full scan; hybrid scheme; observability; sequential circuits; test application time; test vectors; transition faults; Circuit faults; Circuit testing; Controllability; DH-HEMTs; Design for testability; Electrical fault detection; Fault detection; Hybrid power systems; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE

Conference_Location

Atlantic City, NJ, USA

Print_ISBN

0-7803-0623-6

Type

conf

DOI

10.1109/VTEST.1992.232724

Filename

232724