On the effectiveness of simultaneous self-test techniques

Describes a built-in self-test (BIST) technique for general sequential circuits in which storage elements in a circuit are replaced with self-test elements. These elements are connected as a feedback shift register, and used to both generate test patterns and compress test responses. Benchmarks were run on a number of standard sequential benchmark circuits to determine single stuck-at fault coverage. The results of these tests indicate that the self-test techniques presented obtain fault coverage similar to that of random test techniques.<>