Title :
Built-in self-test design for large embedded PLAs
Author :
Pierzynska, Alicja ; Pilarski, Slawomir
Author_Institution :
Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
Abstract :
Proposes a new easily testable PLA. In the design process the authors use a simple property of relatively prime numbers. The PLA can be efficiently integrated with random pattern techniques used for testing combinational circuits. In the proposed implementation, test pattern generation and test response compaction are performed by circular self-test path (circular BIST). Very high fault coverage can be achieved in a feasible testing time.<>
Keywords :
built-in self test; design for testability; logic arrays; logic testing; circular BIST; circular self-test path; embedded PLAs; fault coverage; random pattern techniques; relatively prime numbers; test pattern generation; test response compaction; testable PLA; testing time; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Combinational circuits; Compaction; Performance evaluation; Process design; Programmable logic arrays; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-7803-0623-6
DOI :
10.1109/VTEST.1992.232727
