Title :
Robust switch-level test generation
Author :
Mathew, Ben ; Saab, Daniel G.
Author_Institution :
Illinois Univ., Urbana, IL, USA
Abstract :
Metal oxide semiconductor (MOS) technology is highly popular currently due to the many advantages that it provides. It has been shown that conventional methods of testing are not applicable to MOS circuits. A switch-level model is used to generate a sequence of test vectors for a variety of MOS circuits, including those containing pass transistor logic.<>
Keywords :
MOS integrated circuits; integrated circuit testing; integrated logic circuits; logic testing; MOS circuits; pass transistor logic; robust test generation; switch-level model; test vectors; Circuit faults; Circuit testing; Feedback circuits; Logic gates; Logic testing; MOS devices; MOSFETs; Power semiconductor switches; Robustness; Switching circuits;
Conference_Titel :
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-7803-0623-6
DOI :
10.1109/VTEST.1992.232733
