Automated symbolic optimization and high level synthesis of single- and multi- band digital pre-distortion hardware in an FPGA

This paper presents an automated approach to optimizing the Volterra series digital predistortion (DPD) hardware implementation in field-programmable gate array (FPGA). First, a symbolic tool is used to carry out a number of arithmetic transformations and optimize the model´s expression. Next, automated fixed-point conversion and high level synthesis (HLS) tools are used to generate the hardware description language (HDL) code of single- and dual-band Volterra series DPDs. The proposed approach was first applied to implement a single-band Volterra DPD, in an FPGA, and linearize a 45 W single-ended GaN power amplifier (PA) driven by a 20 MHz LTE signal. The same approach was applied to implement a dual-band Volterra DPD and to linearize the same PA driven by a dual band signal composed of 101 Wideband Code Division Multiple Access (WCDMA) and 15 MHz Long Term Evolution (LTE) components.