DocumentCode
3288605
Title
On fault deletion problem in concurrent fault simulation for synchronous sequential circuits
Author
Kim, Kyuchull ; Sajuja, K.K.
Author_Institution
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
fYear
1992
fDate
7-9 April 1992
Firstpage
125
Lastpage
130
Abstract
A method for improving the performance of concurrent fault simulators for combinational and synchronous sequential circuits is proposed. The paper identifies two causes of inefficiencies and a simple and uniform method to eliminate them. A simulator, FASTS, based on the method proposed in the paper is implemented and it is shown that FASTS outperforms the existing concurrent simulation methods proposed in literature.<>
Keywords
combinatorial circuits; fault location; logic CAD; logic testing; sequential circuits; FASTS; combinational circuits; concurrent fault simulation; fault deletion problem; synchronous sequential circuits; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Fault detection; Sequential analysis; Sequential circuits; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location
Atlantic City, NJ, USA
Print_ISBN
0-7803-0623-6
Type
conf
DOI
10.1109/VTEST.1992.232736
Filename
232736
Link To Document