Design of reduced testing for VLSI circuits based on linear code theory

Pseudo-exhaustive testing can detect all stuck-at faults in combinational circuits. Although the testing time is reduced compared to exhaustive testing, it still remains long. In this paper, a design procedure which requires a minimum number of test vectors to detect all stuck-at faults is presented. The process is based on linear code theory, and different generator polynomials are used to design the LFSR. Fault simulation is used to evaluate the faults detected by each test vector generated consecutively by the LFSR. The LFSR resulting in a minimum number of test vectors is chosen for circuit implementation. The results show that this approach greatly reduces the test time of the actual circuit.<>