A new technique for totally self-checking CMOS circuit design for stuck-on and stuck-off faults

Author

Cheema, Manjit S. ; Lala, P.K.

Author_Institution

Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA

fYear

1992

fDate

7-9 April 1992

Firstpage

155

Lastpage

159

Abstract

Presents a new technique for designing single stage fully complementary metal oxide semiconductor (FCMOS) and CMOS domino logic circuits so that they are totally self checking for all single s-off and s-on faults. It involves the encoding of the output of the circuit in an error detecting code. CMOS circuits designed using the technique have two outputs. Two of the combinations (01,10) are considered to be valid code-words. The circuit is augmented such that any stuck-off (stuck-on) fault in the modified circuit produces a non-valid output 11(00), thus ensuring automatic fault detection.<>

Keywords

CMOS integrated circuits; built-in self test; error detection codes; fault location; integrated logic circuits; logic testing; FCMOS; automatic fault detection; domino logic circuits; encoding; error detecting code; fully complementary; stuck-off faults; stuck-on faults; totally self-checking CMOS circuit; valid code-words; Automatic testing; CMOS logic circuits; Circuit faults; Circuit synthesis; Circuit testing; Clocks; Digital systems; Electrical fault detection; Logic circuits; Logic testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE

Conference_Location

Atlantic City, NJ, USA

Print_ISBN

0-7803-0623-6

Type

conf

DOI

10.1109/VTEST.1992.232741

Filename

232741