Title :
A concurrent checking scheme for single and multibit errors in logic circuits
Author :
Kolla, B. ; Lala, P.K. ; Yarlagadda, K.C.
Author_Institution :
Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
Abstract :
A new scheme for detecting single and multibit (unidirectional and bidirectional) errors using residue codes has been proposed. This procedure has been applied to circuits with outputs up to 8 bits. It has been shown that about 99% of all multibit errors can be detected using this scheme.<>
Keywords :
VLSI; built-in self test; fault location; integrated logic circuits; logic testing; bidirectional errors; concurrent checking scheme; logic circuits; multibit errors; residue codes; single errors; unidirectional errors; Bidirectional control; Circuit faults; Circuit testing; Costs; Electrical fault detection; Fault detection; Logic circuits; Monitoring; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-7803-0623-6
DOI :
10.1109/VTEST.1992.232742
