The impact of mechanical stress control on VLSI fabrication process

Fabrication process is designed to minimize mechanical stress in semiconductor devices and to improve device reliability. Mechanical stress levels were predicted by simulation then TEM analysis was performed to evaluate critical stress that generates dislocations. This gives us design guidelines for small geometry LOCOS process. Polysilicon thickness in the W polycide gate electrode is designed to minimize mechanical stress in the gate oxide and to suppress gate oxide failure in probe and class tests. Moreover, critical stress to generate dislocations during post source/drain ion implantation anneal is obtained by a ball indentation method. This indicated that lower temperature anneal is effective to suppress dislocations. Two-step anneal is introduced to suppress dislocations to enable higher ion activation.