Title :
Optimum redundancy design for new-generation EPROMs based on yield analysis of previous generation
Author :
Imamiya, Ken-ichi ; Miyamoto, Jun-ichi ; Ohtuska, N. ; Tomita, Naoto ; Iyama, Yumiko
Author_Institution :
Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
Failure modes of 4 Mbit EPROMs have been analyzed, and the model to formulate them is proposed. The redundancy scheme of a 16 Mbit EPROM was optimized by the model in consideration of area penalty. In applying the 4 Mbit data to 16 Mbit EPROM, fabrication line improvement was taken into account. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction. The 16 Mbit EPROM has 2 rows*8 blocks redundancy, and the redundancy gives the highest yield in the time when the mass production begins.<>
Keywords :
EPROM; VLSI; circuit reliability; failure analysis; integrated memory circuits; redundancy; 16 Mbit; 4 Mbit; EPROMs; area penalty; fabrication line improvement; failure analysis; mass production; redundancy scheme; yield analysis; Circuit faults; Design engineering; EPROM; Failure analysis; Laboratories; Manufacturing; Mass production; Redundancy; Semiconductor devices; Testing;
Conference_Titel :
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-7803-0623-6
DOI :
10.1109/VTEST.1992.232746
