Title :
Probe point insertion for at-speed test
Author :
Rudnick, Elizabeth M. ; Chickermane, Vivek ; Patel, Janak H.
Author_Institution :
Center for Reliable & High-Performance Comput., Illinois Univ., Urbana, IL, USA
Abstract :
Some recent studies show that an at-speed sequential or functional test is better than a test executed at lower speed. Design-for-testability approaches based on full scan, partial scan, or silicon-based solutions like Crosscheck achieve very high stuck-at fault coverage. However, in all these cases, the tests have to be applied at speeds lower than the operation speed. In this paper, a design-for-test method which permits at-speed testing is introduced. The method is based on probe point insertion for improved observability. Improvements in fault coverage were made for all 16 of the ISCAS-80 benchmark circuits studied. Fault coverages between 99% and 100% were obtained for six circuits, and 100% ATG efficiency achieved on all but two circuits.<>
Keywords :
automatic testing; design for testability; fault location; logic testing; probes; ATG efficiency; Crosscheck; DFT; ISCAS-80 benchmark circuits; at-speed test; fault coverage; full scan; functional test; operation speed; partial scan; probe point insertion; sequential test; stuck-at fault coverage; Automatic testing; Circuit faults; Circuit testing; Fault detection; Logic testing; Observability; Probes; Semiconductor device testing; Sequential analysis; Sequential circuits;
Conference_Titel :
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-7803-0623-6
DOI :
10.1109/VTEST.1992.232756
