Title :
Redundancy removal and simplification of combinational circuits
Author :
Menon, P.R. ; Ahuja, Hitesh
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
Redundancy in combinational circuits is usually identified when faults are found to be undetectable during test generation. Redundancy removal based on test generation is not efficient, because removal of the redundancy causing a fault to be undetectable will usually affect the detectability of other faults, making it necessary to repeat test generation. The authors present a method of identifying and removing redundancy in combinational circuits by analyzing regions between fanout stems and reconvergence gates, and experimental results for the ISCAS85 benchmark circuits.<>
Keywords :
combinatorial circuits; logic design; logic testing; redundancy; ISCAS85 benchmark circuits; combinational circuits; fanout stems; reconvergence gates; redundancy removal; test generation; Benchmark testing; Character generation; Circuit analysis; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Fault diagnosis; Redundancy;
Conference_Titel :
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-7803-0623-6
DOI :
10.1109/VTEST.1992.232764
