Title :
Path-based next trace prediction
Author :
Jacobson, Quinn ; Rotenberg, Eric ; Smith, James E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Abstract :
The trace cache is proposed as a mechanism for providing increased fetch bandwidth by allowing the processor to fetch across multiple branches in a single cycle. But to date predicting multiple branches per cycle has meant paying a penalty in prediction accuracy. We propose a next trace predictor that treats the traces as basic units and explicitly predicts sequences of traces. The predictor collects histories of trace sequences (paths) and makes predictions based on these histories. The basic predictor is enhanced to a hybrid configuration that reduces performance losses due to cold starts and aliasing in the prediction table. The Return History Stack is introduced to increase predictor performance by saving path history information across procedure call/returns. Overall, the predictor yields about a 26% reduction in misprediction rates when compared with the most aggressive previously proposed, multiple branch prediction methods
Keywords :
cache storage; computer architecture; instruction sets; performance evaluation; Return History Stack; aliasing; fetch bandwidth; histories; hybrid configuration; misprediction rates; multiple branches; next trace predictor; path based next trace prediction; path history information; performance losses; prediction accuracy; prediction table; predictor performance; procedure call/returns; trace cache; trace sequences; Accuracy; Assembly; Bandwidth; Computer science; History; Jacobian matrices; Parallel processing; Performance loss; Prediction methods; Proposals;
Conference_Titel :
Microarchitecture, 1997. Proceedings., Thirtieth Annual IEEE/ACM International Symposium on
Conference_Location :
Research Triangle Park, NC
Print_ISBN :
0-8186-7977-8
DOI :
10.1109/MICRO.1997.645793