Title :
Effective concurrent test for a parallel-input multiplier using modulo 3
Author :
Debany, W.H. ; Macera, A.R. ; Daskiewich, D.E. ; Gorniak, M.J. ; Kwiat, K.A. ; Dussault, H.B.
Author_Institution :
Rome Lab., RL/ERDA, Griffiss AFB, NY, USA
Abstract :
Experiments were performed to determine the effectiveness of modulo 3 checking for a class of two´s complement, parallel-input multipliers. A full gate-level simulation of stuck-at faults was performed. The probability of aliasing for a 12*12-bit multiplier was found to be only 5.196%. The assumption that bit errors are statistically-independent yields a much greater probability of aliasing.<>
Keywords :
digital arithmetic; fault location; logic testing; multiplying circuits; probability; aliasing probability; bit errors; concurrent test; gate-level simulation; modulo 3 checking; parallel-input multiplier; stuck-at faults; Circuit faults; Data processing; Error correction; Laboratories; Military standards; Predictive models; Process control; Signal processing; Testing; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-7803-0623-6
DOI :
10.1109/VTEST.1992.232766
