Title :
Zero cost testing of check bits in RAMs with on-chip ECC
Author :
Ramanathan, P. ; Saluja, K.K. ; Franklin, M.
Author_Institution :
Wisconsin Univ., Madison, WI, USA
Abstract :
The authors address the problem of testing the check bits in RAMs with on-chip ECC. A solution is proposed in which the check bits are tested in parallel with the testing of the information bits. The solution entails finding parity-check matrices such that all the check bits are tested while the information bits are being tested, without any increase in the length of the test sequence. The resulting parity-check matrix is such that there is no loss in error-correction capabilities and with minimal penalty in the worst-case delay of the error-correcting logic.<>
Keywords :
error correction codes; integrated circuit testing; integrated memory circuits; matrix algebra; random-access storage; RAMs; check bits; error-correcting logic; error-correction capabilities; on-chip ECC; parity-check matrix; zero cost testing; Computer errors; Costs; Delay; Error correction codes; Logic design; Logic testing; Manufacturing; Parity check codes; Random access memory; Read-write memory;
Conference_Titel :
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-7803-0623-6
DOI :
10.1109/VTEST.1992.232768
