New design-to-test software strategies accelerate time-to-market

Today´s growing device complexity and new manufacturing requirements have presented significant challenges for manufacturers looking to speed time-to-market. One such challenge is the need to contain test costs, of which a major component is the time and resources required for test program development. Some test development tools that exist today can translate a device´s functional events and scan patterns into test programs for targeted ATE. Identification and specification of critical timing parameters that require conversion into cycle-based ATE formats have become an increasing cost factor, which can also significantly impact test accuracy. Traditionally, timing specifications from microprocessor and IP cores, multiple bus types, and other device components can be established via published timing specifications and by a manageable, iterative process between design and test engineering. Likewise, automatic test pattern generation tools for structural test can address simple timing, and are capable of generating cycle-based timing. Today´s complex SoC may consist of over 60 IP cores made more complicated by increased challenges from high-speed serial bus technology and multiple-time domain designs. Further complicating test program development is the need for compatibility with multiple ATE platforms to accommodate global manufacturing strategies. Next generation design-to-test software tools have to address these factors to help reduce the ever growing cost-of-test. Tools must support standard industry test languages such as standard test interface language (STIL), support both functional events and scan patterns, and validate outputs to ensure first-pass success of test programs pre- and post silicon, across multiple ATE platforms.