A new tool for random testability evaluation using simulation and formal proof

Author

Simeu, E. ; Puissochet, A. ; Rainard, J.-L. ; Tagant, A.M. ; Poize, M.

Author_Institution

CNET, Meylan, France

fYear

1992

fDate

7-9 April 1992

Firstpage

321

Lastpage

326

Abstract

A set of tools is described, allowing one to compute random testability measurement for combinational circuits, based on a black box worst case hypothesis. These tools provide enough information to allow circuit modification, in order to meet a prescribed testability value. The efficiency of these tools is due to the use of a statistical method combined with formal proof mechanisms. The random testability of the complete ISCAS benchmark of combinational circuits is computed. For the least testable circuits, a few modifications, guided by the testability measurements, are shown to be sufficient to make them randomly testable.<>

Keywords

combinatorial circuits; logic testing; simulation; statistical analysis; ISCAS benchmark; combinational circuits; random testability evaluation; simulation; statistical method; Benchmark testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Semiconductor device modeling; Switching circuits; Telecommunication computing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE

Conference_Location

Atlantic City, NJ, USA

Print_ISBN

0-7803-0623-6

Type

conf

DOI

10.1109/VTEST.1992.232773

Filename

232773