Title :
Improving the theory of truth table verification of iterative logic arrays
Author :
Nicolaidis, Michael
Author_Institution :
IMAG/TIM3, Grenoble, France
Abstract :
The author shows that, if the number of the states of the reduced flow table of an iterative logic array (ILA) is not a power of 2, then, the truth table verification of the ILA requires to test it exhaustively. Thus, in this case the theory presented by F.J.O. Dias (1976) and allowing the truth table verification of ILAs by means of C-tests, is not valid. Then the author extends this theory to the case where the ILA cells have some inputs in common (such ILAs are for instance ALUs, and the rows of multiply and divide arrays).<>
Keywords :
logic arrays; logic testing; C-tests; iterative logic arrays; reduced flow table; truth table verification; Adders; Circuit faults; Circuit testing; Logic arrays; Power system reliability; Sequential circuits; System testing;
Conference_Titel :
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-7803-0623-6
DOI :
10.1109/VTEST.1992.232776
