A Novel R-C Combination Based Pseudo-differential SAR A/D Converter in 90nm CMOS Process

A 10-bit 3 Ms/s 90 nm CMOS SAR A/D converter is presented in this paper. Pseudo-differential comparison architecture is utilized to improve the performance, where the errors caused by clock feed-through and charge injection can be considered as common-mode interferences. Instead of traditional voltage scaling architecture, an R-C combination based D/A converter is used to reduce the chip area. And due to the inherent S/H function of its capacitor array, no additional S/H circuit is needed. To achieve good matching performance, each unit resistor is sided by dummies and the capacitors are routed with a common-central symmetry method. This converter fabricated in SMIC 90 nm CMOS process occupies an area of 217 um times 220 um. With a 3.3 V analog supply and a 1.0 V digital supply, the measured DNL and INL are 0.33 LSB and 0.74 LSB respectively. With a 2.7 MHz input signal sampled at 3 Ms/s, the power dissipation is measured to be 12.08 mW and the SFDR and ENOB are 62.97 dB and 9.38 Bits respectively.