DocumentCode
328925
Title
A new approach to via minimization problem in VLSI chip design
Author
Yong, Seong ; Kim, Won Gyoum ; Han, Mun-sung ; Lee, Won Don
Author_Institution
Dept. of Comput. Sci., Chung Nam Nat. Univ., Taejon, South Korea
Volume
2
fYear
1993
fDate
25-29 Oct. 1993
Firstpage
1495
Abstract
Hopfield neural networks (HNN) and simulated annealing (SA) are two recent approaches to solving many combinatorial optimization problems. But, the disadvantages of HNN are that it can often converge at local minimum and the quality of solutions depends on the initial state because of sensitivity of parameterization. On the other hand, SA is designed to cope with the problem of convergence to a local minimum. SA, however, requires unacceptably large computing time. So, a new algorithm called mean field annealing (MFA) which can be interpreted as a generalization of HNN, is applied to optimization problems efficiently. In this paper, we propose a new approach based on MFA to solving of the minimization problem. Also we show that our approach can be applied to multi-layer as well as two-layer routing, and optimal solutions can be obtained by properly adjusting the parameter in the given energy function.
Keywords
Hopfield neural nets; VLSI; circuit CAD; convergence of numerical methods; integrated circuit design; minimisation; network routing; simulated annealing; Hopfield neural networks; VLSI chip design; combinatorial optimization; convergence; energy function; mean field annealing; minimization; multi-layer routing; simulated annealing; two-layer routing; Chip scale packaging; Educational institutions; Hopfield neural networks; Integrated circuit interconnections; Intelligent networks; Minimization; Systems engineering and theory; Topology; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on
Print_ISBN
0-7803-1421-2
Type
conf
DOI
10.1109/IJCNN.1993.716828
Filename
716828
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