Test and debug techniques for multiple clock domain SoC devices

As semiconductor processes go beyond 90mm, system-on-chip (SoC) devices with multiple buses tends to be non-integer multiples of each other and possibly asynchronous. In order to mimic the end applications, the ATE system needs to provide a test environment as close to the native operation as possible. SoC devices have had multiple clock domains for some time now, and solutions to testing them with a dual-time domain system have been previously published in A.T Sivaram (2001). Debugging a microprocessor often presents a number of challenges to the test engineer based on D. Josephson (2002). The task becomes much more challenging with SoC devices that include more than two clock domains, and the added complexity of dealing with high-speed serial buses, which are faster than 400 Mbit. The traditional solutions have been to simulate and test these devices, with their clocks set up as an integer multiple of one another, so that they would fit within ATE restrictions. Certain test systems allow patterns to be split into separate timing domains, where each group of tester pins runs at a separate non-integer rate. Recently, the opportunity presented itself to work with a north bridge device with both single and multi-domain patterns available running at high speed. Using this project as a case study, this paper presents the key issues that need to be managed for successfully testing a multi-domain device. High-speed testing demands more up-front documentation from design prior to fixture layout. This paper highlights the necessity of mastering the suite of common ATE diagnostic tools and oscilloscope techniques to resolve problems during the test development of a case study device.