DocumentCode :
3289372
Title :
The implementation of an out-of-order execution floating point unit
Author :
Min, Luo ; Yong-Qiang, Bai ; Xu-Bang, Shen ; De-Yuan, Gao
Author_Institution :
NorthWestern Polytech. Univ., Xi´´an, China
Volume :
2
fYear :
2004
fDate :
18-21 Oct. 2004
Firstpage :
1384
Abstract :
The prRISC32 FPU (floating-point unit) is a RISC coprocessor for embedded system applications. It supports IEEE754 standard single/double precision floating-point addition, floating-point subtraction, floating-point multiplication, floating-point division, floating-point square root, floating-point/fix-point format conversion, and floating point load/store, etc. It also supports four IEEE compliant rounding mode, and precise exception. It can execute and complete instructions out of order under certain cases. Commercial 0.18μm 1P6M standard cell library was used to reduce design time and expense. The prototype chip was operated at about 300 MHz and with the worst-case operating conditions can be operated at about 250MHz in post-route simulation.
Keywords :
IEEE standards; coprocessors; embedded systems; floating point arithmetic; reduced instruction set computing; 0.18 micron; 1P6M standard cell library; 250 MHz; IEEE compliant rounding mode; IEEE754 standard; RISC coprocessor; embedded system; out-of-order execution floating point unit; prRISC32 FPU; single/double precision floating-point addition; Computational modeling; Coprocessors; Degradation; Delay; Embedded system; Libraries; Out of order; Pipelines; Scientific computing; Virtual prototyping;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
Type :
conf
DOI :
10.1109/ICSICT.2004.1436816
Filename :
1436816
Link To Document :
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