DocumentCode :
3289382
Title :
Near void-free no-flow underfill flip chip on board assembly technology reliability characterization
Author :
Colella, Michael ; Baldwin, Daniel
Author_Institution :
George W. Woodruff Sch. of Mech. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear :
2004
fDate :
July 14-16, 2004
Firstpage :
223
Lastpage :
228
Abstract :
A hybrid process has been developed that combines a capillary underfill flow dynamic with no-flow fluxing underfills to result in near void-free assemblies. This new hybrid no-flow process is reviewed in this work. Reliability analysis of test vehicles assembled with the new hybrid process is presented and compared with the conventional no flow underfill process. The development of this process has potential to avoid the problem of early solder extrusion into underfill voids during reliability testing or during a potential use condition. The overall reliability performance for the new process is determined in order to insure that the process can be used effectively in a production environment. This work evaluates the reliability of parts assembled with the newly developed hybrid process. Test boards were assembled according to an optimal process developed for four commercially available no-flow underfills. Two reliability tests were used to evaluate the new process. Accelerated reliability tests performed included air/air thermal cycling (AATC) and autoclave tests. The newly developed edge patterned hybrid no-flow process has resulted in near void-free assemblies capable of passing 2000 cycles without failure for the -40 to 125°C thermal cycle reliability test.
Keywords :
adhesives; assembling; flip-chip devices; integrated circuit reliability; integrated circuit testing; soldering; -40 to 125 C; air-air thermal cycling; autoclave tests; capillary underfill flow dynamic; early solder extrusion; edge patterned hybrid no-flow process; hybrid process; near void-free assembly; no-flow fluxing underfills; no-flow underfill process; optimal process; production environment; reliability analysis; reliability characterization; reliability performance; test boards; test vehicles; thermal cycle reliability testing; underfill flip chip on board assembly; underfill voids; void-free flip chip on board assembly; Assembly; Electronic packaging thermal management; Flip chip; Integrated circuit interconnections; Laboratories; Mechanical engineering; Paper technology; Semiconductor device modeling; Testing; Vehicle dynamics;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Manufacturing Technology Symposium, 2004. IEEE/CPMT/SEMI 29th International
ISSN :
1089-8190
Print_ISBN :
0-7803-8582-9
Type :
conf
DOI :
10.1109/IEMT.2004.1321666
Filename :
1321666
Link To Document :
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