DocumentCode :
3289420
Title :
Soft gold electroplating from a non-cyanide bath for electronic applications
Author :
Wang, Kai ; Beica, Rozalia ; Brown, Neil
Author_Institution :
Rohm & Haas Electron. Mater., Freeport, NY, USA
fYear :
2004
fDate :
July 14-16, 2004
Firstpage :
242
Lastpage :
246
Abstract :
The electrodeposition of pure gold is an enabling technology for wafer bump and wire bonding interconnects applications. Most conventional pure gold electroplating processes used in the electronics industry are cyanide based. Due to the toxicity of the free cyanide formed during electrolysis, as well as cyanide´s incompatibility with positive photoresists, sulfite-based gold processes have been the traditional alternative for wafer applications. However, traditional sulfite-based processes have suffered from issues with solution stability and the necessity for annealing to achieve the desired deposit hardness. This paper describes a stable non-cyanide process that can be used for soft gold electroplating. Electrochemical characterization of two non-cyanide processes is presented to illustrate the electrochemical behaviour of gold in the presence of different complexing agents. The effects of operating parameters on process performance, including cathode efficiency, deposit purity, hardness, solderability and solution stability are presented. The thickness uniformity, surface morphology and topography of the electrodeposited gold bumps, as well as wire bonding performance, are also presented.
Keywords :
electrolysis; electroplating; integrated circuit interconnections; lead bonding; photoresists; soldering; surface morphology; surface topography; cathode efficiency; complexing agents; deposit purity; electrochemical behaviour; electrochemical characterization; electrodeposited gold bumps; electronic applications; gold electrodeposition; interconnect hardness; noncyanide bath; positive photoresists; soft gold electroplating; solderability; solution stability; stable noncyanide process; sulfite-based gold process; surface morphology; surface topography; thickness uniformity; wafer bump; wire bonding interconnects; wire bonding performance; Annealing; Cathodes; Electrochemical processes; Electronics industry; Gold; Resists; Stability; Surface morphology; Wafer bonding; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Manufacturing Technology Symposium, 2004. IEEE/CPMT/SEMI 29th International
ISSN :
1089-8190
Print_ISBN :
0-7803-8582-9
Type :
conf
DOI :
10.1109/IEMT.2004.1321669
Filename :
1321669
Link To Document :
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