Title :
A low-cost, robust method to vertical sidewalls for thick resists processing
Author :
Hamel, Clifford J.
Author_Institution :
SUSS MicroTec, Inc., Waterbury Center, VT, USA
Abstract :
In the realm of wafer level packaging (WLP), chip scale packaging (SCP), micro-electronic machines (MEM´s), etc. the ebb and flow of lithographic upgrades takes on a very important role. Any improvement than can be made at the lowest possible cost has a significant impact on the final cost of the device. Today, feature size, profile of the resist feature, and overall control of the process are now considered critical parameters for back end of line (BEOL) processes. Current lithographic procedures typically utilized 1X full field lithography (1XFFL) tools in proximity print mode to generate images for BEOL processes. In the past, some production facilities have considered alternate, more expensive methods to generate smaller feature sizes. One method under renewed consideration is contact exposure using full field lithography equipment. Although, contact exposure is a technically capable and proven imaging technology it is expensive due to the increased levels of defects and increased levels of defects and increased costs due to frequent mask-cleaning cycles. Mask cleaning may be reduced or eliminated by using a Teflon coated mask, however, many people still believe this is not a viable alternative for vertical slide walls on thick films. There now is a low cost, robust alternative. By making a small change to existing 1XFFL tools, imaging capability can be significantly improved to accommodate current and future needs of BEOL processes. Images with vertical sidewall profiles in films 5 to 100 microns thickness may be produced effortlessly using proximity exposure. Thickness changes affecting dose as seen with standard processes are also minimized.
Keywords :
lithography; resists; 1XFFL tools; 5 to 100 microns; Teflon coated mask; chip scale packaging; critical parameters; full field lithography equipment; imaging capability; imaging technology; lithographic procedures; lithographic upgrades; low-cost method; mask-cleaning cycles; micro-lectronic machines; process control; proximity print mode; resist feature; robust method; thick resists processing; vertical sidewalls; wafer level packaging; Chip scale packaging; Costs; Image generation; Lithography; Process control; Production facilities; Resists; Robustness; Size control; Wafer scale integration;
Conference_Titel :
Electronics Manufacturing Technology Symposium, 2004. IEEE/CPMT/SEMI 29th International
Print_ISBN :
0-7803-8582-9
DOI :
10.1109/IEMT.2004.1321670