Title :
Parallel test reduces cost of test more effectively than just a cheap tester
Author_Institution :
Agilent Technol. R&D, Boeblingen, Germany
Abstract :
Today´s manufacturers of high-volume consumer devices are under tremendous cost pressure and consequently under extreme pressure to reduce cost of test. Low-cost ATE has often been promoted as the obvious solution. Parallel test is another well-known approach, where multiple devices are tested in parallel (multi-site test) and/or multiple blocks within one device are tested in parallel (concurrent test). This paper shows quantitatively that parallel test is a much effective test cost reduction method than low-cost ATE, because it reduces all test cost contributors, not only capital cost of ATE. It also shows that the optimum number of sites is relatively insensitive to ATE capital cost, operating cost, yield, and various limiting factors, but the cost benefits diminish fast, if limited independent ATE resources reduce the degree of parallelism and force a partially sequential test.
Keywords :
automatic test equipment; integrated circuit economics; integrated circuit testing; production testing; ATE capital cost; ATE operating cost; I-O bandwidth matching; concurrent test; cost of test reduction; high-volume consumer devices; low-cost ATE; multisite testing; parallel testing; probe card; reduced pin-count testing; test economics; Cost function; Manufacturing; Power generation economics; Production; Research and development; Semiconductor device manufacture; Semiconductor device modeling; Sequential analysis; Testing; Transistors;
Conference_Titel :
Electronics Manufacturing Technology Symposium, 2004. IEEE/CPMT/SEMI 29th International
Print_ISBN :
0-7803-8582-9
DOI :
10.1109/IEMT.2004.1321674