DocumentCode
3289522
Title
EBIST: a novel test generator with built-in fault detection capability
Author
Pradhan, Dhiraj K. ; Liu, Chunsheng ; Chakraborty, Krish
Author_Institution
Bristol Univ., UK
fYear
2003
fDate
2003
Firstpage
224
Lastpage
229
Abstract
A novel design methodology for test pattern generation in BIST is presented. Here, faults and errors in the generator itself are detected. Two different design methodologies are presented. The first one guarantees all single fault/error detection and the second methodology is capable of detecting multiple faults and errors. Furthermore the proposed LFSRs do not have additional hardware overhead. Also, importantly, the test patterns generated have the potential to achieve superior fault coverage.
Keywords
automatic test pattern generation; built-in self test; fault location; fault simulation; logic design; logic testing; shift registers; BIST; EBIST; LFSR; built-in fault detection; fault coverage; fault simulation; multiple faults/errors detection; single fault/error detection; test pattern generation; Built-in self-test; Circuit faults; Circuit testing; DH-HEMTs; Design methodology; Fault detection; Hardware; Logic testing; Manufacturing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2003
ISSN
1530-1591
Print_ISBN
0-7695-1870-2
Type
conf
DOI
10.1109/DATE.2003.1186390
Filename
1186390
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