Author_Institution :
Johnstech Int. Corp., Minneapolis, MN, USA
Abstract :
As semiconductor device bandwidth, speed, functionality and resolution continue to climb, it becomes more obvious that the whole test system must be optimized to achieve the highest yields at the lowest cost per device and insertion. The overall system performance depends not only on the automated test equipment (ATE), but equally on the on the interfacing between the ATE, the device under test (DUT) and the IC handling equipment. Everything must interface properly and predictable, both electrically and mechanically. If any single part of the system produces nonrepeatable results, then the measurements taken on the device will not be repeatable. Because of the high visibility of capital, many organizations and their test engineers underestimate the contributions from the relatively inexpensive pieces to the test puzzle, specifically the contactor, the load board, and the mechanical interfacing between the ATE and handler (docking). This paper will provide a framework for understanding the relationships between the elements, demonstrating the importance of the DUT interface, and will present an engineering approach to maximizing yield through optimizing the whole system. Detailed examples will follow, showing how this approach is applied to the critical interface parts of the system. The significant benefits to be gained by using modeling and simulation will be discussed. Numerous examples of the successful correlation of modeled and measured data will be presented. The combined efforts of modeling and measurement will show details such as device package tolerances, lead or pad plating or how long a device sits in production before testing can impact test yields and costs. Modeling will also be shown to help reduce costly board redesigns, obtain true device performance, calibrate the system, and ensure repeatability of measurements taken in production. This paper will conclude by showing how RF bandwidth, signal integrity, and grounding can be improved by choosing the correct materials for items such as contactors and load boards. In addition, data will be shown that optimizing the load board and contactor can allow devices to be retested more quickly and more accurately, thus improving first pass yields and reducing the need for retesting failed devices in pr- oduction.
Keywords :
automatic test equipment; contactors; integrated circuit testing; integrated circuit yield; modelling; optimisation; production testing; simulation; ATE-handler mechanical interfacing; DUT interface; IC handling equipment; RF bandwidth; automated test equipment; contactor optimization; costly board redesigns; device package tolerance; device under test; functionality; grounding; lead plating; load board optimization; low test costs; measurement repeatability; modeling; optimal yields; pad plating; resolution; semiconductor device; signal integrity; simulation; speed; system calibration; test system optimization; yield maximization; Automatic testing; Bandwidth; Cost function; Integrated circuit testing; Packaging; Semiconductor device testing; Semiconductor devices; System performance; System testing; Test equipment;