An alternative printing solution to sphere placement for second level interconnect assembly

Semiconductor packaging devices, such as μBGA and WCSPs, continue to challenge assembly processes. In the second level interconnect process sphere attach systems commonly used today are reaching processes limitations, particularly with today\´s shrinking package designs. Limitations are reached when sphere diameters reach below 0.30mm (0.012"). smaller packaging designs and tighter pitch requirements are calling for smaller sphere diameters, down to 0.020mm(0.010") and below, which begins to challenge these robotic sphere placement systems. Flux application, sphere handling, and placement accuracy requirement become more difficult to achieve, affecting process reliability and overall yields. As pitch and bump height requirements decrease, second level interconnect technologies begin to overlap into flip-chip wafer bumping process, such as electroplating and photo-stencil printing. However, these processes are expensive and capital-intensive for second level interconnects assembly. A process solution and lower cost alternative to sphere placement exists in traditional solder paste stencil printing, commonly used in SMT assembly. The challenge with stencil printing lies with achieving proper solder pastes deposits at extremely tight pitches. Current stencil design rules and aperture ratios (area of the aperture opening/area of the wall area >0.66) limit the ability to print acceptable deposits at extremely tight pitches without any bridging or defects. Recent work has proven that applying a high frequency low amplitude vibration to the stencil rules, improves solder pastes transfer efficiency, and produces higher solder volume deposits at extremely tight pitches. This paper will investigate enhanced release printing applied to second level interconnect assemblies, such as interconnect pitches, bump height ranges, and co-planarity will be presented, in addition to the effects on stencil design and solder paste formulation.