A low device occupation IP to implement Rijndael algorithm [cryptography]

This work presents a soft IP description of Rijndael, the advanced encryption standard (AES) of the National Institute of Standards and Technology (NIST). This Rijndael implementation runs its symmetric cipher algorithm using a key size of 128 bits, called the AES128 mode. The focus here is to produce a low area IP achieving good performance. To do that, we propose an architecture using mixed bit size processing, leading to a significant decrease in memory usage. The same methodology is used to implement three versions: the first one only encrypts the data, the second one decrypts and the third one performs both operation on the same device. The implementation choice was the AcexlK and Cyclone devices of Altera. The paper presents an introduction to cryptography, the AES contest that defined Rijndael as the new standard, the AES128 structure and some results, such as device occupation, clock frequency, throughput and latency.