• DocumentCode
    3290159
  • Title

    A proposal for transaction-level verification with Component Wrapper Language

  • Author

    Ara, Koji ; Suzuki, Kei

  • Author_Institution
    Central Res. Lab., Hitachi Ltd., Tokyo, Japan
  • fYear
    2003
  • fDate
    2003
  • Firstpage
    82
  • Abstract
    We propose a new approach to accelerate transaction level verification by raising the productivity of the verification suites including test patterns, protocol checker, and simulation-coverage analyzer This approach combines the conventional transaction level language such as C and the signal level language based on our previously developed Component Wrapper Language (CWL). This approach is based on two concepts. The first one is a complete separation between transaction-level verification and signal-level verification for generating suitable verification suites in each design phase. The second one is the quick generation of signal-level verification suites from the original specification written in CWL. Experimental results show that our approach should yield much shorter verification periods versus conventional methods.
  • Keywords
    digital simulation; formal verification; protocols; Component Wrapper Language; protocol checker; signal level language; signal-level verification; signal-level verification suites; simulation-coverage analyzer; test patterns; transaction-level verification; verification periods; verification suites; Analytical models; Life estimation; Pattern analysis; Productivity; Proposals; Protocols; Signal analysis; Signal design; Signal generators; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition, 2003
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-1870-2
  • Type

    conf

  • DOI
    10.1109/DATE.2003.1186676
  • Filename
    1186676