Unified Matrix Processor Design for FCT-IV and FST-IV Hartley Based Transforms

Author

Hamarsheh, Qadri

Author_Institution

Dept. of MIS, Philadelphia Univ., Amman

fYear

2006

fDate

24-27 May 2006

Firstpage

151

Lastpage

156

Abstract

A new unified fast shifted cosine and sine transform matrix processor based on fast Hartley transform is presented and described. It is also shown that the decimation-in-frequency (DIF) FCT-IV and FST-IV can be computed using the same building blocks which are used for computing decimation-in-time FCT-IV and FST-IV. A unified fast shifted cosine and sine transform matrix processor can be designed to compute either the DCT-IV or DST-IV

Keywords

discrete Hartley transforms; discrete cosine transforms; matrix algebra; DCT-IV; DST-IV; FCT-IV; FST-IV; Hartley based transforms; decimation-in-frequency; discrete cosine transform; discrete sine transform; fast shifted cosine transform; fast shifted sine transform; unified matrix processor; Data compression; Discrete cosine transforms; Discrete transforms; Frequency domain analysis; HDTV; Image coding; Matrix converters; Process design; Symmetric matrices; Transform coding; Discrete Cosine Transform; Discrete Sine Transform; Hartley Transform and FCT-IV and FST-IV algorithms; Matrix Processor;

fLanguage

English

Publisher

ieee

Conference_Titel

Perspective Technologies and Methods in MEMS Design, 2006. MEMSTECH 2006. Proceedings of the 2nd International Conference on

Conference_Location

Lviv

Print_ISBN

966-553-517-X

Type

conf

DOI

10.1109/MEMSTECH.2006.288687

Filename

4068451