• DocumentCode
    3290473
  • Title

    A framework for balancing control flow and predication

  • Author

    August, David I. ; Hwu, Wen-Mei W. ; Mahlke, Scott A.

  • Author_Institution
    Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
  • fYear
    1997
  • fDate
    1-3 Dec 1997
  • Firstpage
    92
  • Lastpage
    103
  • Abstract
    Predicated execution is a promising architectural feature for exploiting instruction-level parallelism in the presence of control flow. Compiling for predicated execution involves converting program control flow into conditional, or predicated, instructions. This process is known as if-conversion. In order to effectively apply if-conversion, one must address two major issues: what should be if-converted and when the if-conversion should be applied. A compiler´s use of predication as a representation is most effective when large amounts of code are if-converted and if-conversion is performed early in the compilation procedure. On the other hand the final code generated for a processor with predicated execution requires a delicate balance between control flow and predication to achieve efficient execution. The appropriate balance is tightly coupled with scheduling decisions and detailed processor characteristics. This paper presents an effective compilation framework that allows the compiler to maximize the benefits of predication as a compiler representation while delaying the final balancing of control flow and predication to schedule time
  • Keywords
    instruction sets; optimising compilers; parallel architectures; parallel programming; program control structures; scheduling; software performance evaluation; compiler; conditional instructions; if-conversion; instruction-level parallelism; parallel architecture; predicated execution; predicated instructions; program control flow; schedule time; scheduling decisions; Computer aided instruction; Concurrent computing; Delay effects; Hardware; Laboratories; Optimizing compilers; Parallel processing; Performance gain; Processor scheduling; Uncertainty;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microarchitecture, 1997. Proceedings., Thirtieth Annual IEEE/ACM International Symposium on
  • Conference_Location
    Research Triangle Park, NC
  • ISSN
    1072-4451
  • Print_ISBN
    0-8186-7977-8
  • Type

    conf

  • DOI
    10.1109/MICRO.1997.645801
  • Filename
    645801