A digital calibration algorithm for pipelined ADC

Due to the limitation of non-ideal factors such as gain error, capacitor mismatch and offset, resolution of pipelined ADC is limited to 10 bits below. Focusing on it, this paper presents a digital calibration algorithm based on voltage threshold of comparator in every stage for pipelined ADC. This method improves pipelined ADC´s performance by injecting calibration reference into pipelined ADC, extracts transform error and calibrates the output digital of the ADC in digital domain. Simulation results based on Matlab model of a 12bits 50Ms/s pipelined ADC shows the resolution has improved obviously.